Latches

---

Latches and flip-flops are memory elements that store a single bit of data. They are crucial for building static random access memory (SRAM) and CPU registers.

• Latches are level-triggered — their outputs change immediately when inputs change.
• Flip-flops are edge-triggered — outputs only change on a clock signal's rising or falling edge. This makes them essential for synchronizing components in a CPU.

All the designs that follow are extensions of this foundation — the building blocks of a register file.

SR Latches

The most basic type of latch. SR latches have two input signals: Set (S) and Reset (R). The output Q is the stored memory state, while Q' (Q complement) is the opposite.

Behavior:

• S = 1, R = 0: Sets Q to 1.
• S = 0, R = 1: Resets Q to 0.
• S = 0, R = 0: Holds the current state.
• S = 1, R = 1: Undefined behavior (Q and Q' both being 1 is impossible).

Here’s a typical SR latch circuit and its truth table:

Gated SR Latches

What if we wanted to control when the latch updates its memory? By adding two AND gates alongside the set and reset signals, we introduce an enable signal. This lets us choose when the latch updates:

• Enable = 1: Latch works as normal (Set and Reset respond).
• Enable = 0: Output holds the previous state, ignoring Set and Reset.

D Latches

A D latch simplifies the gated SR latch by combining the Set and Reset inputs into one data input (D). It prevents invalid states by ensuring S and R are always opposites internally.

• When E = 0 (Latch Mode): The output (Q) remains unchanged, holding the last stored value.
• When E = 1 (Transparent Mode): The output follows the input (Q = D), meaning Q updates directly based on D.
• The complement output (Q) is always the opposite of Q, ensuring only one of them is high at a time.

This behavior makes the D-latch useful for temporary data storage in registers and memory elements.

Everything is NAND

Fun fact: every latch we’ve covered — SR, Gated SR, and D latches — has a NAND gate equivalent! Can you figure out how to build them? They behave similarly but use NAND gates instead of NOR gates.

Note: For this class, we won’t cover JK or T latches — but feel free to explore those on your own!

D Flip-Flops

D Flip-Flops build on D latches by introducing a clock pulse, ensuring the output only updates on a rising or falling edge of the clock signal.

Let’s break this down:

• 1’s and 0’s: Represented as high and low voltage states respectively.
• Pulses: Short-duration current signals that transition between high and low states.
• Clock pulses: These special pulses synchronize CPU components. They transition from low-to-high-to-low (rising edge) or high-to-low-to-high (falling edge).
• Minecraft comparison: Think of pulses as redstone ticks or pulse generators. You’ll see these when we trigger a write signal!

D Flip-Flops are ideal for CPU registers because they only update precisely when the clock pulse triggers — ensuring reliable, synchronized data flow. The below is an example of a 2 tick pulse, that triggers when the button is pressed. We will talk more about pulses and clocks in the program counters section of this textbook.

In Minecraft

The beauty of Minecraft is that they gave us a mechanism for storing memory. Although there are many different practices, we primarily rely on the data-latch or d-latch. A d-latch is a simple way to hold data in place. You can construct one with two repeaters, where one repeater "locks" the other one. When the repeater lock is established, any input data will not affect what is stored in memory. When the repeater lock is released, the data slot can be updated at will. You can think of this as choosing when or when to not hit save on a file.

Here is an example of a d-latch in three different setups. Try it yourself.